Semiconductor device and manufacturing method and operating method for the same

ABSTRACT

A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high threshold voltage channel region is formed in the first well and extending down from the surface of the substrate.

BACKGROUND

1. Technical Field

The disclosure relates in general to a semiconductor device and a methodfor manufacturing and operating the same, and more particularly to adepletion metal-oxide-semiconductor device and method for manufacturingand operating the same.

2. Description of the Related Art

The depletion metal oxide semiconductor has one character: when thevoltage from gate to source is zero, a channel exists and it provides aoutput current. However, the current of the conventional depletion MOSis constant, it can't be scalable on the same device area and process.Therefore, the depletion MOS can't be applied for different circuit.

SUMMARY

The disclosure is directed to a semiconductor device and a method formanufacturing and operating the same. The output current of thesemiconductor could be scale base on demand.

According to one embodiment, a semiconductor device is provided. Asemiconductor device comprises a substrate, a deep well, a first well, afirst doped electrode region, a second doped electrode region and a highthreshold voltage channel region. The substrate has a first typeconductivity. The deep well is formed in the substrate and has a secondtype conductivity opposite to the first type conductivity. The firstwell is formed in the deep well and has at least one of the first typeconductivity and the second type conductivity. The first doped electroderegion and the second doped electrode regions are formed in the firstwell. The first doped electrode region has the first type conductivity.The second doped electrode is adjacent to the first doped electrode andhas the second type conductivity. The high threshold voltage channelregion is formed in the first well, extends down from a surface of thesubstrate, covers parts of a surface of the second doped electrode andhas the second type conductivity. A surface of the high thresholdvoltage channel having a first side, a second side opposite to the firstside, a third side and the fourth side opposite to the third side, thefirst side and the second side are adjoined to the third side and thefourth side.

According to another embodiment, a method for manufacturingsemiconductor device is provided. First, a substrate having a first typeconductivity is provided. A deep well having a second type conductivityopposite to the first type conductivity is formed in the substrate andextending down from a surface of the substrate. A first well having atleast one of the first type conductivity and the second typeconductivity is formed in the deep well and extending down from thesurface of the substrate. A high threshold voltage channel region havingthe second type conductivity is formed in the first well and extendingdown from the surface of the substrate. A first doped electrode regionhaving the first type conductivity is formed in the deep well whereinthe first doped electrode region is in a region without the highthreshold voltage channel region in the first well. A second dopedelectrode region having the second type conductivity is formed in thedeep well. The second doped electrode region is adjacent to the firstdoped electrode region, and parts of the second doped electrode regionare covered by the high threshold voltage channel region. An outputcurrent of the semiconductor device is scaled according to a ratio thatthe high threshold voltage channel region covered by the second dopedelectrode region.

According to an alternative embodiment, a method for operatingsemiconductor device is provided. The semiconductor device comprises asubstrate, a deep well, a first well, a first doped electrode region, asecond doped electrode region, a third doped electrode region and a highthreshold voltage channel region. The substrate has a first typeconductivity. The deep well is formed in the substrate and has a secondtype conductivity opposite to the first type conductivity. The firstwell is formed in the deep well and has at least one of the first typeconductivity and the second type conductivity. The first doped electroderegion is formed in the first well and has the first type conductivity.The second doped electrode region is formed in the first well, adjacentto the first doped electrode region and has the second typeconductivity. The third doped electrode region is formed within the deepwell, extending down from a surface of the substrate, spaced apart fromthe second doped electrode region with a distance and has the secondconductive type. The high threshold voltage channel region is formed inthe first well, extends down from the surface of the substrate, coversparts of a surface of the second doped electrode and has the second typeconductivity. The surface of the high threshold voltage channel has afirst side, a second side opposite to the first side, a third side andthe fourth side opposite to the third side, the first side and thesecond side are adjoined to the third side and the fourth side. Theoperating method for the semiconductor device comprises following steps:a voltage is applied to the gate structure. The first doped electroderegion is coupled to a first electrode. The first electrode is one of ananode and a cathode. The third doped electrode region is coupled to asecond electrode. The second electrode is another of the anode and thecathode.

The above and other aspects of the disclosure will become betterunderstood with regard to the following detailed description of thenon-limiting embodiment(s). The following description is made withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates top views of a semiconductor device according to oneembodiment of the disclosure.

FIG. 1B is a partial enlarging drawing of FIG. 1A.

FIG. 2 is a cross-sectional view along the cross-sectional line A-A′ ofFIG. 1B.

FIG. 3 is a cross-sectional view along the cross-sectional line B-B′ ofFIG. 1B

FIG. 4A is relationship between the drain current and the drain voltageat different covered angle of the high threshold voltage channel region.

FIG. 4B is a partial enlarging drawing of FIG. 4A.

FIG. 5A is a partial enlarging top view of another semiconductor deviceaccording to the embodiment of the disclosure.

FIG. 5B is an alternative enlarging top view of another semiconductordevice according to the embodiment of the disclosure.

FIG. 6A-FIG. 14B depict a process of manufacturing the semiconductordevice of the embodiment.

In the following detailed description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of the disclosed embodiments. It will be apparent,however, that one or more embodiments may be practiced without thesespecific details. In other instances, well-known structures and devicesare schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

FIG. 1A illustrates top views of a semiconductor device according to oneembodiment. FIG. 1B illustrates an enlarged view of a portion, indicatedby a dotted line, of the semiconductor device shown in FIG. 1A. In oneembodiment, the semiconductor structure 10 comprises a first well 13formed in a deep well of a substrate. The first well 13 includes twoadjacent doped electrode regions, that is, a first doped electroderegion 14 and a second doped electrode region 15. A high thresholdvoltage channel region 132 has a first side 132 a, a second side 132 bopposite to the first side, a third side 132 c and a fourth side 132 dopposite to the third side. The first side 132 a and the second side 132b are adjoined to the third side 132 c and the fourth side 132 d, whichforms a closed area. The high threshold voltage channel region 132covers parts of the second doped electrode region 15. In thisembodiment, a semiconductor device with the annular electrodes formed onthe substrate. The invention is not limited to the annular electrodes,and other shapes (viewed from top) of electrodes could be constructed.For example, partial electrodes could be plural strips arranged inparallel.

In embodiments, the substrate 11 and the first doped electrode region 14have a first type conductivity such as P type conductivity, while thedeep well 12, the second doped electrode region 15 and the highthreshold voltage region 132 have a second type conductivity such as Ntype conductivity, opposite to the first type conductivity. And viceversa. The first well 12 could have at least one of the first typeconductivity and the second type conductivity.

Please refer to FIG. 2 and FIG. 3 for illustrations of the embodiment.FIG. 2 is a cross-sectional view along the cross-sectional line A-A′ ofFIG. 1B, and FIG. 3 is a cross-sectional view along the cross-sectionalline B-B′ of FIG. 1B. The difference between FIGS. 2 and 3 is theexistence of the high threshold voltage channel region 132.

Specifically, the first doped electrode 14 and the second dopedelectrode 15 is adjacently disposed in the first well. In the structureof FIG. 2, the high threshold voltage channel region 132 is extendingdown from a surface of the substrate 11 and covering parts of a surfaceof the second doped electrode 15. In addition, a field layer 131 is alsoextend down from the surface of the substrate 11, and covering parts ofa surface of the first doped electrode 14. The field layer has a firsttype conductivity. On the other hand, there is no high threshold voltagechannel region in the structure of FIG. 3. The field layer 131 coversthe surface of the first doped electrode 14 and the second dopedelectrode 15. That is, the high threshold voltage channel region 132covers parts of the second doped electrode region 15, and the fieldlayer 131 cover the other parts of the second doped electrode region 15and all the first doped electrode region 14.

As shown in FIG. 2 and FIG. 3, the semiconductor device 10 comprises athird doped electrode region 16, a top doped region 19, the dielectric18 and a gate structure 17, wherein the top doped region 19 has thefirst type conductivity and the third doped electrode region 16 has thesecond type conductivity. The third doped electrode region 16 is formedwithin the deep well 12 and spaced apart from the second doped electroderegion 15 with a distance. The dielectric 18 is formed on the substrate11 and positioned between the second doped electrode region 15 and thethird doped electrode region 16. The dielectric 18 could be a fieldoxide (FOX). The top doped region 19 is formed in the deep well 12 andpositioned beneath the dielectric 18. The gate structure 17 is disposedon the high threshold voltage channel region and the dielectric.

As shown in FIG. 2 and FIG. 3, the semiconductor device 10 furthercomprises an inter-layered dielectric (ILD) 21 formed on the surface ofthe substrate 11 and exposing partial surfaces of the field layer 131,the third doping electrode region 16 and the gate structure 17. Thesemiconductor device 10 further comprises a first electrode 22, a secondelectrode 23 and a third electrode 24 formed on the ILD 21 andcontacting said exposed partial surfaces of the field layer 131, thethird doping electrode region 16 and the gate structure 17,respectively. In embodiment, the first electrode 22 is electricallyconnected to the first doped electrode region 14 and the second dopedelectrode region 15. The second electrode 23 is electrically connectedto the third doped electrode region 16. The third electrode 24 iselectrically connected to the gate structure 17. In one embodiment, thesemiconductor device is a depletion MOS device. The three electrodescould be used as the anode (source), cathode (drain) or gate of thedepletion MOS device.

In one embodiment, an output current provided by the semiconductordevice 10 can be controlled by adjusting an area of the second dopedelectrode region 15 covered by the high threshold voltage channel region132. For example, please referring to FIG. 4A and FIG. 4B, whichillustrating relationship between the drain current and the drainvoltage at different covered angle of the high threshold voltage channelregion. The measurement results show that the higher covered angle θ is,which means an area of the second doped electrode region covered by thehigh threshold voltage channel region is higher, the high drain current(output current) of the semiconductor device 10 is. When θ=360°, whichmeans the high threshold voltage channel region 132 covers all theannular second doped electrode region, the drain current is maximum.

In one embodiment, as shown in FIG. 5A, there could be 2 or more highthreshold voltage channel regions 132 in the semiconductor device 10.The size of each high threshold voltage channel regions 132 may bedifferent. The intensity of output current is decided by the total areaof the second doped electrode region 15 covered by the high thresholdvoltage channel region 132, such as θ₁+θ₂+θ₃+θ₄. . . . In thisembodiment, the covered angle θ of each high threshold voltage channelregions is different, wherein θ₁<θ₂<θ₃<θ₄. In other embodiment, thespaced angle α between each of the high threshold voltage channelregions is different, as shown in FIG. 5B, wherein α₁<α₂<α₃<α₄.

FIG. 6A-FIG. 14B depict a process of manufacturing the semiconductordevice of the embodiment. Figures labeled with A such as FIGS. 6A, 7A,8A, . . . 14A illustrate a cross-sectional view along thecross-sectional line A-A′ of FIG. 1B, wherein the position of thecross-sectional line A-A′ is corresponding to the first well 13 with thehigh threshold voltage channel region 132. Figures labeled with B suchas FIGS. 6B, 7B, 8B, . . . 14B illustrate cross-sectional view along thecross-sectional line B-B′ of FIG. 1B, wherein the position of thecross-sectional line B-B′ is corresponding to the first well 13 withoutthe high threshold voltage channel region 132.

Also, P type and N type are selected as the first type conductivity(i.e. conductivity of the substrate 11 and the first doped electroderegion 14) and the second type conductivity (i.e. conductivity of thedeep well 12 and the second doped electrode region) for marking in thedrawings. However, the invention is not limited thereto.

Please refer to FIG. 6A and FIG. 6B. First, a substrate 11 having afirst type conductivity is provided, and a deep well 12 having a secondtype conductivity is formed in the substrate 11 by ion implant, and thedeep well 12 extends down from the surface of the substrate 11. Next, afirst well 13 is formed in the deep well 12 and extending down from thesurface of the substrate 11 by ion implant. The first well 23 could haveat least one of the first type conductivity and the second typeconductivity and in this embodiment the first well has bothconductivities. Also, other P-well (PW) could be formed outside the deepwell 12.

Please refer to FIG. 7A and FIG. 7B. A top doped region 19 having thefirst type conductivity is formed in the deep well 12 by implant.

Please refer to FIG. 8A and FIG. 8B. A field layer 131 having the firsttype conductivity is formed in the first well 13 and extending down fromthe surface of the substrate 11 by ion implant. The size of the fieldlayer 131 in FIG. 8A is smaller than it in FIG. 8B.

Please refer to FIG. 9A and FIG. 9B. A dielectric 18 such as filed oxide(FOX) is formed on the substrate 11 and positioned above the top dopedregion 19. Examples of the dielectric 18 include FOX and shallow trenchisolation (STI).

Please refer to FIG. 10A and FIG. 10B. A high threshold voltage layer132 having the second type conductivity is formed in the first well 13,adjacent to the field layer 131 and extending down from the surface ofthe substrate 11 by ion implant.

Please refer to FIG. 11A and FIG. 11B. A gate structure 170 is formed onthe high threshold voltage region 132, and extended on the dielectric18. The gate structure 17 may comprise a gate dielectric layer, a gateelectrode layer and a spacer. The gate electrode layer is formed on thegate dielectric layer. The spacers are formed on opposite sidewalls ofthe gate dielectric layer and the gate electrode layer. In oneembodiment, before forming the gate dielectric layer, a SAC oxide isformed on the surface of the substrate 104, and then the SAC oxide isremoved. Therefore, the gate dielectric layer having excellent propertycan be formed. The gate electrode layer may comprise a polysilicon layerand a metal silicide layer, such as tungsten silicide, formed on thepolysilicon layer. The spacer may comprise silicon dioxide such astetraethoxy silane (TEOS).

Please refer to FIG. 12A and FIG. 12B. A first doping electrode region14 having the first type conductivity is formed in the first well 23, asecond doping electrode region 15 having the second type conductivity isformed in the first well 23 and a third doping electrode region 16having the second type conductivity is simultaneously formed in the deepwell 12 by ion implant. The first doping electrode region 14 is adjacentto the second doping electrode region 15. The third doped electroderegion 16 is extending down from the surface of the substrate 11, andspaced apart from the second doped electrode region 15 by dielectric 18.In FIG. 12A, the first doped electrode region 14 is formed beneath thefield layer 131, and the second doped electrode region 15 is formedbeneath the high threshold voltage channel region 132.

Please refer to FIG. 13A and FIG. 13B. By dielectric formation, patterndefining and etching, an inter-layered dielectric (ILD) 21 is formed onthe surface of the substrate 11 and exposes partial surfaces of thefield layer 131, the high threshold voltage channel region 132, thethird doping electrode region 16 and the gate structure 17.

Please refer to FIG. 14A and FIG. 14B. A conductive layer is depositedon the substrate 11 and patterned by photo-define and etching, to form afirst electrode 22, a second electrode 23 and a third electrode 24 onthe ILD 21. The first electrode 22, the second electrode 23 and thethird electrode 24, filling up the openings of the ILD 21, contact theexposed partial surfaces of the field layer 131 (first electrode 22),the high threshold voltage channel region 132 (first electrode 22), thethird doping electrode region 16 (second electrode 23) and the gatestructure 17 (third electrode 24), respectively. The first electrode 22,the second electrode 23 and the third electrode 24 could function assource (anode), drain (cathode) and gate of the semiconductor device inthe application.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the disclosed embodiments.It is intended that the specification and examples be considered asexemplary only, with a true scope of the disclosure being indicated bythe following claims and their equivalents.

What is claimed is:
 1. A semiconductor device, comprising: a substratehaving a first type conductivity; a deep well formed in the substrateand having a second type conductivity opposite to the first typeconductivity; a first well formed in the deep well, wherein the firstwell has at least one of the first type conductivity and the second typeconductivity; a first doped electrode region formed in the first welland having the first type conductivity; a second doped electrode regionhaving the second type conductivity, wherein the second doped electrodeis formed in the first well and adjacent to the first doped electroderegion; a high threshold voltage channel region formed in the first welland having the second type conductivity, wherein the high thresholdvoltage channel extends down from a surface of the substrate and coversparts of a surface of the second doped electrode, wherein a surface ofthe high threshold voltage channel having a first side, a second sideopposite to the first side, a third side and the fourth side opposite tothe third side, the first side and the second side are adjoined to thethird side and the fourth side.
 2. The semiconductor device according toclaim 1, further comprising at least two the high threshold voltagechannel region.
 3. The semiconductor device according to claim 1,further comprising: a field layer formed in the first well and havingthe first type conductivity, wherein the field layer extends down fromthe surface of the substrate and covers a surface of the first dopedelectrode.
 4. The semiconductor device according to claim 3, furthercomprising: a third doped electrode region within the deep well andhaving the second conductive type, wherein the third doped electroderegion extends down from the surface of the substrate and being spacedapart from the second doped electrode region with a distance.
 5. Thesemiconductor device according to claim 4, further comprising: adielectric formed on the substrate and positioned between the seconddoped electrode region and the third doped electrode region.
 6. Thesemiconductor device according to claim 5, further comprising: a gatestructure on the high threshold voltage channel region and thedielectric.
 7. The semiconductor device according to claim 6, whereinthe gate structure is electrically connected to a voltage source, whenthe voltage source applies zero voltage to the gate structure, thesemiconductor device provides an output current, wherein the higher areaof the second doped electrode region covered by the high thresholdvoltage channel region, the higher output current the semiconductordevice provides.
 8. The semiconductor device according to claim 6,further comprising: a top doped region having the first typeconductivity, wherein the top doped region is formed in the deep welland positioned beneath the dielectric.
 9. A method for manufacturingsemiconductor device, comprising: providing a substrate having a firsttype conductivity; forming a deep well having a second type conductivityopposite to the first type conductivity in the substrate, wherein thedeep well extends down from a surface of the substrate; forming a firstwell having at least one of the first type conductivity and the secondtype conductivity in the deep well, wherein the first well extends downfrom the surface of the substrate; forming a high threshold voltagechannel region having the second type conductivity, wherein the highthreshold voltage channel region is formed in the first well and extendsdown from the surface of the substrate; forming a first doped electroderegion having the first type conductivity in the deep well, wherein thefirst doped electrode region is in a region without the high thresholdvoltage channel region in the first well; forming a second dopedelectrode region having the second type conductivity in the deep well,wherein the second doped electrode region is adjacent to the first dopedelectrode region, and parts of the second doped electrode region arecovered by the high threshold voltage channel region; wherein an outputcurrent provided by the semiconductor device is controlled by adjustingan area of the second doped electrode region covered by the highthreshold voltage channel region.
 10. The method for manufacturingsemiconductor device according to claim 9, wherein a surface of the highthreshold voltage channel having a first side, a second side opposite tothe first side, a third side and a fourth side opposite to the thirdside, the first side and the second side are adjoined to the third sideand the fourth side.
 11. The method for manufacturing semiconductordevice according to claim 9, wherein the step of forming the highthreshold voltage channel region is performed before the step of formingthe first doped electrode region and the second doped electrode region.12. The method for manufacturing semiconductor device according to claim9, further comprising: forming a field layer having the first typeconductivity in the first well, wherein the first well extends down fromthe surface of the substrate and covers a surface of the first dopedelectrode.
 13. The method for manufacturing semiconductor deviceaccording to claim 12, wherein the step of forming the field layer isperformed before the step of forming the first doped electrode regionand the second doped electrode region.
 14. The method for manufacturingsemiconductor device according to claim 12, further comprising: forminga third doped electrode region within the deep well and having thesecond conductive type, wherein the third doped electrode region extendsdown from the surface of the substrate and being spaced apart from thesecond doped electrode region with a distance.
 15. The method formanufacturing semiconductor device according to claim 14, furthercomprising: forming a dielectric on the substrate, wherein thedielectric is positioned between the second doped electrode region andthe third doped electrode region.
 16. The method for manufacturingsemiconductor device according to claim 15, further comprising: forminga gate structure on the high threshold voltage channel region and thedielectric.
 17. The method for manufacturing semiconductor deviceaccording to claim 16, wherein the gate structure is electricallyconnected to a voltage source, when the voltage source applies zerovoltage to the gate structure, the semiconductor provides an outputcurrent.
 18. The method for manufacturing semiconductor device accordingto claim 16, further comprising: forming a top doped region having thefirst type conductivity, wherein the top doped region is formed in thedeep well and positioned beneath the dielectric.
 19. An operating methodfor a semiconductor device, wherein the semiconductor device comprises:a substrate having a first type conductivity; a deep well formed in thesubstrate and having a second type conductivity opposite to the firsttype conductivity; a first well formed in the deep well and having atleast one of the first type conductivity and the second typeconductivity; a first doped electrode region formed in the first welland having the first type conductivity; a second doped electrode regionhaving the second type conductivity, wherein the second dope electroderegion is formed in the first well and adjacent to the first dopedelectrode region; a third doped electrode region formed within the deepwell, wherein the third doped electrode region extends down from thesurface of the substrate, being spaced apart from the second dopedelectrode region with a distance and having the second conductive type;a high threshold voltage channel region having the second typeconductivity, extending down from the surface of the substrate andformed in the first well, the high threshold voltage channel coversparts of the surface of the second doped electrode, wherein a surface ofthe high threshold voltage channel having a first side, a second sideopposite to the first side, a third side and a fourth side opposite tothe third side, the first side and the second side are adjoined to thethird side and the fourth side; the operating method for thesemiconductor device comprises: applying a voltage to the gatestructure; coupling the first doped electrode region to a firstelectrode, wherein the first electrode is one of an anode and a cathode;and coupling the third doped electrode region to a second electrode,wherein the second electrode is another of the anode and the cathode.20. The operating method for a semiconductor device according to claim19, wherein the semiconductor device provides an output current when thevoltage is zero.